(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of creating a polysilicon fuse such that the fuse is not damaged by process steps of etch and photoresist remove.
(2) Description of the Prior Art
One of the methods that is typically applied for the further extension and use of created semiconductor devices is to create one or more fuses as part of the semiconductor device creation process. By selectively interrupting or “blowing” these fuses, circuit functions can be provided after basic device features have been created over the surface of a substrate. Defective devices can be selectively removed or new devices can be created, based on device failure analysis results, by creating new paths of electrical conductivity within a semiconductor device. The objective of this procedure of creating and using fuses over the surface of a substrate, over which concurrently multiple additional semiconductor devices have been created, is to minimize device failures by optimally using functional units or sections thereof.
Specifically, fuses can be used to rewire memory and logic semiconductor devices. By for instance blowing fuses that are associated with identified defective memory cells, these defective memory cells can be removed as actively functional units and can at the same time be replaced with created spare rows or columns of memory cells that have been created for the purpose of replacement. Relating to logic devices, it is not uncommon and more cost-effective to create, for certain device functions and applications, generic logic chips, which can in their original design perform a number of different logic functions. For these logic devices to perform a specific logic function, one or more fuses are typically blown, thus in effect creating a more personalized semiconductor device that now performs a more specialized logic function. This approach allows for creating a number of specific logic chips from a generic chip, thereby providing a significant cost reduction of the created logic devices.
It is well known in the art that the increased complexity of semiconductor devices brings with it an increased complexity in the layers of interconnect metal that must be created overlying active devices in order to interconnect these devices. For this reason it is not uncommon to see from two to four overlying layers of interconnect metal created in overlying layers of Intra Level Dielectric (ILD) and Inter Metal Dielectric (IMD). The above referred to process of blowing one or more fuses to further affect the creation of a functional semiconductor device requires that these fuses are accessible to exposure for purposes of heating the fuse by for instance exposure to a laser beam. This requires that an opening must be created aligned with the fuse or fuses so that the energy that is provided by the laser beam can adequately heat the fuse or fuses that must be interrupted. It is clear from this that the process of creating openings that are aligned with one or more fuses, in view of the multiple layers of IMD and ILD that are typically created overlying the fuses, can be cumbersome and may be difficult to control. It is critical that etching of the overlying layers of dielectric does not damage the fuse, this potential damage to a fuse may prematurely open the fuse thereby defeating the purpose of creating the fuse.
Fuses that are used for the above highlighted objectives of device creation can be made using either doped or undoped polysilicon or can be made using metal. The invention specifically addresses aspects of creating polysilicon fuses and the problems encountered therewith. It can thereby generally be stated that as an objective of creating a fuse comprising polysilicon that this fuse should be created such that the fuse is exposed for blowing thereof without however having incurred any damage to the fuse in the process that is required to expose the fuse. The invention addresses these concerns for a polysilicon fuse.
U.S. Pat. No. 6,124,211 (Butterbaugh et al.) shows a method to remove native oxides.
U.S. Pat. No. 6,255,715 B1 (Liaw) is a related patent.
U.S. Pat. No. 5,306,671 (Ogawa et al.) shows a surface treatment method. This patent provides for forming a film of native oxide over the surface of a silicon substrate, this film is etched by a first plasma etch employing a gas containing fluorine. The surface of the substrate is again subjected to a second plasma etching by employing a gas containing fluorine in order to remove a surface damaged layer and a fluorocarbon layer formed during the above step of first plasma etching. The substrate is then radiated with UV rays under low pressure in order to disassociate and remove fluorine atoms that have chemically interacted with the substrate during the second plasma etching. The instant invention does not apply the methods provided by this patent.
U.S. Pat. No. 5,858,878 (Toda) shows a post etch step.